1. Field of the Invention
The present invention relates to a storage circuit control device and the method thereof, and a graphic computation device and the method thereof, capable of efficiently using the storage area of a storage circuit storing texture data, for example.
2. Description of the Related Art
Computer graphics are often used in various CAD (Computer Aided Design) systems, amusement devices, and so forth. Particularly, recent advancements in image processing technology has given rise to rapid propagation of systems using three-dimensional computer graphics.
With such three-dimensional computer graphics, rendering processing is performed in order to display the graphics on a display such as a CRT (Cathode Ray Tube) having pixels arrayed in matrix fashion.
In this rendering processing, the color data for each pixel is calculated, and the obtained color data is written to a display buffer (frame buffer) corresponding with the pixel. One of the techniques for rendering processing is polygon rendering. With this technique, a three-dimensional model is expressed as a combination of triangular unit shapes (polygons), and drawing is performed in units of these polygons, thereby determining the color. of the display screen.
With three-dimensional computer graphics systems using such polygon rendering, texture mapping processing is performed at the time of drawing. This texture mapping processing reads texture data indicating an image pattern from a texture buffer in units of triangles, and pasts this read texture data onto the surface of the three-dimensional model, so as to obtain highly realistic image data.
With the texture mapping processing, as shown below, a two-dimensional texture address for specifying a pixel projecting an image according to the image data is calculated, and this is used as a texture address to make reference to texture data stored in the texture buffer.
Specifically, first, the (s, t, q) of each pixel within the triangle is calculated from linear interpolation, based on the (s1, t1, q1), (s2, t2, q2), and (s3, t3, q3) indicating the homogeneous coordinates (s, t) of the apexes of the triangle and the homogeneous item q.
Now, in simple terms, the homogeneous item q is the ratio of enlargement or reduction.
Next, division yields the (s/q, t/q) for each pixel, the s/q and t/q are each multiplied by the texture size USIZE and VSIZE, thereby generating texture coordinates data (u, v).
Next, the texture coordinates data (u, v) is converted into a texture address (U, V) on the texture buffer, and this texture address (U, V) is used to read the texture data from the texture buffer.
With three-dimensional computer graphics systems such as described above, the texture data may be stored in a two-dimensional array corresponding to a U and V coordinates system in the storage area of the texture buffer, so that direct reference can be made to the texture buffer using the texture address (U, V). That is to say, the two-dimensional texture address (U, V) may be directly used to access texture data stored in the texture buffer. This method simplifies the processing for accessing the texture data.
However, there is a problem with this method, in that storing multiple types of texture data in the texture buffer results in available area which cannot be efficiently used as shown in FIG. 10, due to the relation between the size of the texture data to be stored and the size of the available area, and consequently the storage area cannot be efficiently used.
For example, as shown in FIG. 10, in the event of storing pieces of texture data 400, 401, 402, 403, and 406, each with differing address lengths in the U and V directions, within the address space of the texture buffer so that direct reference can be made with the texture address (U, V), available areas 410 and 411 where texture data cannot be stored is created due to the relation between the two-dimensional size of the texture data to be stored and the two-dimensional size of the available area.
Consequently, a texture buffer having an extremely great storage capacity in comparison to the amount of texture data to be stored must be used, increasing the scale of the system and raising costs.
Accordingly, conventional systems calculate a one-dimensional physical address A from a two-dimensional texture address (U, V), based on xe2x80x9cphysical address A=Vxc3x97(texture width)+Uxe2x80x9d, and use this physical address A to access the texture buffer, in order to use the storage area of the texture buffer in an efficient manner. Thus, texture data can be stored without creating an available area in the storage area of the texture buffer, as shown in FIG. 11.
Incidentally, xe2x80x9ctexture widthxe2x80x9d refers to the address length in the U direction, in the address space of the texture buffer.
FIG. 12 is a partial configuration diagram of a conventional three-dimensional computer graphic system.
As shown in FIG. 12, the physical address A for each pixel is calculated from the (s1, t1, q1), (S2, t2, q2), and (s3, t3, q3) of the apex of the triangle as described above, in the address converting device 104 built into the texture mapping device 101. Then, using this calculated physical address A, the texture data (R, G, B, xcex1) is read from the texture buffer 102 to the texture mapping device 101, this texture data (R, G, B, xcex1) is pasted to the pixels corresponding to the surface of the three-dimensional model, thereby generating plotting data S101. This plotting data S101 is written to the display buffer 103.
Also, with high-speed three-dimensional computer graphics systems, as shown in FIG. 13 for example, an n number of texture mapping devices 101 through 101n each having built-in address converting devices 1041 through 104n, and texture mapping processing is simultaneously performed for an n number of pixels in a parallel manner, thereby simultaneously writing the plotting data S1011 through S101n to the display buffer.
However, with three-dimensional computer graphics systems such as described above, using the physical address A generated by xe2x80x9cphysical address A=Vxc3x97(texture width)+Uxe2x80x9d to generate one-dimensional physical addresses A from two-dimensional texture addresses (U, V) requires a massive multiplication circuit for performing multiplication according to the xe2x80x9ctexture widthxe2x80x9d. Consequently, this leads to a problem in which the size of the system increases.
Particularly, in cases such as shown in FIG. 13 wherein a plurality of texture mapping devices 1011 through 101n are provided, the problem of circuit size is serious.
The present invention has been made in light of the problems with the above-described conventional art, and accordingly, it is an object of the present invention to provide a storage circuit control device and a graphic computation device capable of efficiently using the storage area of the texture buffer with a small circuit configuration.
It is another object of the present invention to provide a storage circuit control method and a graphic computation method capable of efficiently using the storage area of the texture buffer.
In order to solve the above-described problems with the conventional art, and to achieve the above objects, the storage circuit control device according to the present invention stores in a storage circuit two-dimensional image data indicating color data of a plurality of pixels arrayed in matrix fashion, and accesses the two-dimensional image data stored in the storage circuit using a two-dimensional address (U, V) corresponding to the two-dimensional positioning of the plurality of pixels, the storage circuit control device comprising:
an address generating means for combining the bit data making up the U address of the two-dimensional address (U, V) represented by n bits (wherein n is an integer of 1 or greater) and the bit data making up the V address of the two-dimensional address (U, V) represented by m bits (wherein m is an integer of 1 or greater), so as to generate an (n+m)-bit one-dimensional address; and
a data accessing means for accessing the storage circuit using the generated one-dimensional address.
With the storage circuit control device according to the present invention, at the time of accessing two-dimensional image data stored in the storage circuit, first, the two-dimensional address (U, V) of the pixel data to be accessed is generated, following certain image processing.
Next, at the address generating means, the bit data comprised of the n bits of U and m bits of V making up the generated two-dimensional address (U, V) are combined, so as to generate an (n+m)-bit one-dimensional address.
Next, at the data accessing means, the storage circuit is accessed using the generated one-dimensional address.
The processing in the address generating means with the storage circuit control device according to the present invention is realized with no more than a simple bit operation, and more specifically is realized by the following operations.
That is, more specifically, with the storage circuit control device according to the present invention, in the event that
the integer n and the integer m are equal;
k is an integer expressed by (nxe2x88x921)  less than k  less than 0;
the U address is represented by the n bits of (U [nxe2x88x921], . . . , U [k], . . . , U [0]);
and the V address is represented by the n bits of (V [nxe2x88x921], . . . , V [k], . . . , V [0]);
the address generating means combines each of the bit data U [nxe2x88x921], . . . , U [k], . . . , U [0] of the U address with each of the bit data V [nxe2x88x921], . . . , V [k], . . . , V [0] of the V address, thereby generating 2n bits of one-dimensional addresses (V [nxe2x88x921], U [nxe2x88x921], . . . , V [k], U [k], . . . , V [0], U [0]).
Also, more specifically, with the storage circuit control device according to the present invention, in the event that
the integer m is (nxe2x88x921);
k is an integer expressed by (nxe2x88x921) less than k less than 0;
the U address is represented by the n bits of (U [nxe2x88x921], . . . , U [k], . . . , U [0]);
and the V address is represented by the (nxe2x88x921) bits of (V [nxe2x88x922], . . . , V [k], . . . , V [0]);
the address generating means combines each of the bit data U [nxe2x88x921], . . . , U [k], . . . , U [0] of the U address with each of the bit data V [nxe2x88x922], . . . , V [k], . . . , V [0] of the V address, thereby generating (2nxe2x88x921) bits of one-dimensional addresses (U [nxe2x88x921], V [nxe2x88x922], U [nxe2x88x922], . . . , V [k], U [k], . . . , V [0], U [0]).
Also, with the graphic computation device according to a first aspect of the present invention, a three-dimensional model is represented by a combination of a plurality of unit shapes, and addresses corresponding to the homogeneous coordinates (s, t) and the homogeneous item q included in the image data for each pixel positioned within the unit shapes are used to read texture data which is image data to be pasted to the unit shapes from the storage circuit and perform the pasting thereof to the unit shapes, the graphic computation device comprising:
a storage circuit storing a plurality of pieces of texture data;
a two-dimensional address generating means for generating a two-dimensional address (U, V) comprised of a U address represented by n bits (wherein n is an integer of 1 or greater) and a V address represented by m bits (wherein m is an integer of 1 or greater), based on the results of dividing the homogeneous coordinates (s, t) by the homogeneous item q, i.e., (s/q, s/t);
a one-dimensional address generating means for generating (n+m)-bit one-dimensional addresses by combining the bit data making up the U and V in the two-dimensional addresses (U, V); and
a data reading means for using the generated one-dimensional addresses to read the texture data from the storage circuit, and perform pasting thereof to the unit shapes.
With the graphic computation device according to the first aspect of the present invention, at the two-dimensional address generating means, a two-dimensional address (U, V) comprised of the U address represented by n bits (wherein n is an integer of 1 or greater) and the V address represented by m bits (wherein m is an integer of 1 or greater), based on the results of dividing the homogeneous coordinates (s, t) by the homogeneous item q, i.e., (s/q, s/t).
Next, at the one-dimensional address generating means, (n+m)-bit one-dimensional addresses are generated by combining the bit data making up the U and V in the generated two-dimensional addresses (U, V).
Next, at the data reading means the generated one-dimensional addresses is used to read the texture data from the storage circuit, and perform pasting thereof to the unit shapes.
Also, a graphic computation device according to a second aspect of the present invention comprises:
a storage circuit for storing texture data which is image data to be pasted to unit shapes serving as basic units for expressing the form to be displayed on a display;
a polygon rendering data generating means for generating polygon rendering data regarding the apex of the unit shape, including data for three-dimensional coordinates (x, y, z), R (red), G (green), B (blue), and homogeneous coordinates (s, t) and homogeneous item q;
an interpolation data generating means for interpolating the polygon rendering data for the apex of the unit shape, and generating interpolation data for pixels positioned within the unit shape;
a two-dimensional address generating means for generating a two-dimensional address (U, V) comprised of a U address represented by n bits (wherein n is an integer of 1 or greater) and a V address represented by m bits (wherein m is an integer of 1 or greater), based on the results of dividing the homogeneous coordinates (s, t) contained in the interpolation data by the homogeneous item q, i.e., (s/q, s/t);
a one-dimensional address generating means for generating (n+m)-bit one-dimensional addresses by combining the bit data making up the U and V in the two-dimensional addresses (U, V); and
a data reading means for using the generated one-dimensional addresses to read the texture data from the storage circuit, and perform pasting thereof to the unit shapes.
Also, with the graphic computation device according to the second aspect of the present invention, first, at the polygon rendering data generating means polygon rendering data regarding the apex of the unit shape, including data for three-dimensional coordinates (x, y, z), R (red), G (green), B (blue), and homogeneous coordinates (s, t) and homogeneous item q, is generated.
Next, at the interpolation data generating means, the polygon rendering data is interpolated for the apex of the unit shape, and interpolation data is generated for pixels positioned within the unit shape.
Next, at the two-dimensional address generating means, a two-dimensional address (u, V) comprised of the U address represented by n bits (wherein n is an integer of 1 or greater) and the V address represented by m bits (wherein m is an integer of 1 or greater) is generated, based on the results of dividing the homogeneous coordinates (s, t) contained in the interpolation data by the homogeneous item q, i.e., (s/q, s/t).
Next, at the one-dimensional address generating means, (n+m)-bit one-dimensional addresses are generated by combining the bit data making up the U and V in the generated two-dimensional addresses.
Next, at the data reading means, the generated one-dimensional addresses are used to read the texture data from the storage circuit, and perform pasting thereof to the unit shapes.
Also, a graphic computation device according to a third aspect of the present invention is a graphic computation device wherein a three-dimensional model to be displayed on a display device is represented by a combination of a plurality of unit shapes, and wherein addresses corresponding to the homogeneous coordinates (s, t) and the homogeneous item q included in the image data for each pixel positioned within the unit shapes are used to read texture data which is image data to be pasted to the unit shapes from the storage circuit and perform the pasting thereof to the unit shapes, the graphic computation device comprising:
a polygon rendering data generating device for generating polygon rendering data regarding the apex of the unit shape, including data for three-dimensional coordinates (x, y, z), R (red), G (green), B (blue), and homogeneous coordinates (s, t) and homogeneous item q;
a rendering device for performing rendering processing using the polygon rendering data; and
a bus for connecting the polygon rendering data generating device and the rendering device.
Here, the rendering device comprises:
an interpolation data generating means for interpolating the polygon rendering data of the apex of the unit shape input via the bus, and generating interpolation data for pixels positioned within the unit shape;
a two-dimensional address generating means for generating a two-dimensional address (U, V) comprised of the U address represented by n bits (wherein n is an integer of 1 or greater) and the V address represented by m bits (wherein m is an integer of 1 or greater), based on the results of dividing the homogeneous coordinates (s, t) contained in the interpolation data by the homogeneous item q, i.e., (s/q, s/t);
a one-dimensional address generating means for generating (n+m)-bit one-dimensional addresses by combining the bit data making up the U and V in the two-dimensional addresses; and
a data reading means for using the generated one-dimensional addresses to read the texture data from the storage circuit, and perform pasting thereof to the unit shapes.
With the graphic computation device according to the third aspect of the present invention, first, at the polygon rendering data generating means, polygon rendering data regarding the apex of the unit shape, including data for three-dimensional coordinates (x, y, z), R (red), G (green), B (blue), and homogeneous coordinates (s, t) and homogeneous item q, is generated. This polygon rendering data is transferred to the rendering device via the bus.
Next, the following processing is carried out at the rendering device.
That is, at the interpolation data generating means the polygon rendering data of the apex of the unit shape input via the bus is interpolated, and interpolation data for pixels positioned within the unit shape is generated.
Next, at the two-dimensional address generating means, a two-dimensional address (U, V) comprised of a U address represented by n bits (wherein n is an integer of 1 or greater) and a V address represented by m bits (wherein m is an integer of 1 or greater) is generated, based on the results of dividing the homogeneous coordinates (s, t) contained in the interpolation data by the homogeneous item q, i.e., (s/q, s/t).
Next, at the one-dimensional address generating means, (n+m)-bit one-dimensional addresses are generated by combining the bit data making up the U and V in the generated two-dimensional addresses.
Next, at the data reading means, the generated one-dimensional addresses is used to read the texture data from the storage circuit, and perform pasting thereof to the unit shapes.
Also, the storage circuit control method according to the present invention is a storage circuit control method which stores in a storage circuit two-dimensional image data indicating color data of a plurality of pixels arrayed in matrix fashion, and accesses the two-dimensional image data stored in the storage circuit using a two-dimensional address (U, V) corresponding to the two-dimensional positioning of the plurality of pixels, comprising the steps of:
combining the bit data making up the U address of the two-dimensional address (U, V) represented by n bits (wherein n is an integer of 1 or greater) and the bit data making up the V address of the two-dimensional address (U, V) represented by m bits (wherein m is an integer of 1 or greater) and
accessing the storage circuit using the generated one-dimensional address.
Further, the graphic computation method according to the present invention is a graphic computation method wherein a three-dimensional model is represented by a combination of a plurality of unit shapes, and wherein addresses corresponding to the homogeneous coordinates (s, t) and the homogeneous item q included in the image data for each pixel positioned within the unit shapes are used to read texture data which is image data to be pasted to the unit shapes from the storage circuit and perform the pasting thereof to the unit shapes, comprising the steps of:
storing a plurality of pieces of texture data in a storage circuit;
generating a two-dimensional address (U, V) comprised of the U address represented by n bits (wherein n is an integer of 1 or greater) and the V address represented by m bits (wherein m is an integer of 1 or greater), based on the results of dividing the homogeneous coordinates (s, t) by the homogeneous item q, i.e., (s/q, s/t);
generating (n+m)-bit one-dimensional addresses by combining the bit data making up the U and V in the two-dimensional addresses; and
using the generated one-dimensional addresses to read the texture data from the storage circuit, and perform pasting thereof to the unit shapes.